This is a synthesized time-to-digital converter (TDC), consisting of two wavefront delay rings with a slightly different delay forming a Vernier TDC.
The time between the rising edge of start=ui_in[0] and the rising edge of stop=ui_in[1] is measured by both rings and the output in 8b chunks. Based on analog simulation, the time resolution (typical process, room temperature) is on the order of 6ps.
Apply two signals to ui_in[0] and ui_in[1].
After capturing (rising edge of ui_in[1]) the result (i.e., the time delay between rising edge of ui_in[0] and ui_in[2]) can be muxed-out to uo_out[7:0] using ui_in[7:3] as byte-wise selector. ui_in[7:3]=0000 gives result byte 0, ui_in[7:3]=0001 gives result byte 1, etc.
The input ui_in[2] selects the output of ring 0 or ring 1.
Two signal generators generating the logical signals with a programmable delay (important is ns resolution).
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | Start signal of TDC | Result (LSB) | |
| 1 | Stop signal of the TDC | Result | |
| 2 | Select result of ring for output | Result | |
| 3 | output select (LSB) | Result | |
| 4 | output select | Result | |
| 5 | output select | Result | |
| 6 | output select | Result | |
| 7 | output select (MSB) | Result (MSB) |