We want to design Pulse width Modulation (PWM) with 50MHz input Frequency.
The Verilog code defines a module named tt_um_shivam responsible for generating a Pulse Width Modulation (PWM) signal. It takes a 50MHz clock input (clk) and provides inputs for increasing the assigned pin (ui_in[0]) and decreasing the assigned pin (ui_in[0]) in the duty cycle. The PWM signal is output through the assigned pin PWM_OUT at a frequency of 5MHz.
The code implements debouncing logic for the increase and decrease duty cycle buttons using D flip-flops (DFF_PWM modules) to prevent rapid fluctuations due to button bouncing. It also includes counters for generating slow clock enable signals to facilitate debouncing.
The duty cycle can be adjusted by pressing the increase or decrease buttons, which are debounced to ensure reliable operation. The duty cycle can vary from 0% to 90% (in 10% increments), and the PWM signal is generated based on this duty cycle.
Overall, the code provides a flexible and robust PWM signal generator with adjustable duty cycle control.
We check our design with the help of OpenROAD flow script (ORFS).
default
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | clk | PWM_OUT | |
| 1 | ui_in[0] | ||
| 2 | ui_in[1] | ||
| 3 | |||
| 4 | |||
| 5 | |||
| 6 | |||
| 7 |